AXI Protocol: Architecture, Signal Channels, and Burst Transactions

The AXI (Advanced eXtensible Interface) is a high-performance, burst-based protocol designed for efficient data transfer between components in a system-on-chip. By utilizing a burst-based approach, AXI allows for the transfer of multiple data units, known as beats, for a single request. This architecture is particularly effective when moving large volumes of data to or from specific address patterns, reducing the overhead of repeated address requests.

Key Facts

• Burst-Based: A single request can trigger multiple data transfers (beats).
• Channelized Architecture: Separate channels are used for read and write addresses, data, and responses.
• Handshake Mechanism: Every channel uses a VALID/READY handshake to synchronize data transfer.
• Three Burst Types: Supports FIXED, INCR, and WRAP addressing modes.
• Version Differences: Specific signals vary between AXI3 and AXI4 standards.

AXI Signal Channels

AXI organizes communication into five distinct channels to allow simultaneous read and write operations. Each channel employs a handshake mechanism where the VALID signal indicates the availability of data/information and the READY signal indicates the receiver's ability to accept it.

Address Channels

The Write Address (AW) and Read Address (AR) channels define the parameters of the transaction. Both channels share similar control signals to identify the stream, the starting address, and the nature of the burst.

AXI Address and Control Signals

Function	Write Address (AW)	Read Address (AR)
Stream Identifier	AWID	ARID
Start Address	AWADDR	ARADDR
Burst Length	AWLEN	ARLEN
Beat Size	AWSIZE	ARSIZE
Burst Type	AWBURST	ARBURST
Lock Type (Atomic)	AWLOCK	ARLOCK
Memory Type	AWCACHE	ARCACHE
Protection Type	AWPROT	ARPROT
Quality of Service	AWQOS	ARQOS
Region Identifier	AWREGION	ARREGION
User-defined Data	AWUSER	ARUSER
Handshake Signals	AWVALID / AWREADY	ARVALID / ARREADY

Data and Response Channels

Once the address is established, data is moved via the Write Data (W) and Read Data (R) channels. Finally, the Write Response (B) channel provides the status of write operations.

• Write Data (W): Includes WDATA for the payload, WSTRB (byte strobe) to mark valid bytes, and WLAST to signal the final beat.
• Read Data (R): Includes RDATA for the payload, RRESP for the status of the beat, and RLAST to signal the end of the burst.
• Write Response (B): Uses BRESP to communicate the final status of the entire write burst to the initiator.

Burst Types and Addressing

The burst type determines how the address is calculated for each subsequent beat in a transaction. This is controlled by the ARBURST or AWBURST signals.

FIXED Bursts

In a FIXED burst, every beat uses the same address. This is primarily used for accessing a single memory location repeatedly, such as reading from or writing to a FIFO (First-In, First-Out buffer).

INCR Bursts

INCR (Incrementing) bursts are the most common. Each subsequent beat's address is calculated by adding the transfer size to the previous address, making it ideal for sequential memory access.

WRAP Bursts

WRAP bursts increment the address like INCR bursts, but with a critical difference: if the address reaches a specific "Higher Address boundary," it wraps back to the "Wrap boundary." This is typically used for cache line fills.

: Example of FIXED, INCR and WRAP bursts

Transaction Workflows

Read Transactions

A read operation begins when the initiator provides the start address (ARADDR), burst type (ARBURST), and burst length (ARLEN) on the Read Address channel. Following the ARVALID/ARREADY handshake, the target returns the data on RDATA and the status on RRESP. The target asserts RLAST on the final beat to signal the completion of the request.

: Example of an AXI read transaction. The initiator requests 4 beats (ARLEN + 1[18]) of 4 Bytes each starting from address 0x0 with INCR type. The target returns 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc, all with the OKAY status. Only the most relevant signals are shown here.

Write Transactions

Write operations require the initiator to provide both address and data. The address details (AWADDR, AWBURST, AWLEN) are sent via the Write Address channel. Simultaneously or subsequently, the data is sent via the Write Data channel using WDATA and WSTRB. The initiator asserts WLAST on the final data word. Once both the address and data phases are complete, the target sends a final status update via the BRESP signal on the Write Response channel.

: Example of an AXI write transaction. The initiator drives 4 beats (AWLEN + 1[18]) of 4 Bytes each starting from address 0x0 with INCR type, writing 0x10 for address 0x0, 0x11 for address 0x4, 0x12 for address 0x8 and 0x13 for address 0xc. The target returns 'OKAY' as write response for the whole transaction. Only the most relevant signals are shown here.

Frequently Asked Questions

What is a "beat" in AXI?

A beat is a single data transfer within a larger burst transaction. A burst consists of one or more beats.

How does the AXI handshake mechanism work?

The handshake uses two signals: VALID and READY. A transfer occurs only when both signals are asserted high on the same clock cycle.

What is the purpose of the WSTRB signal?

The WSTRB (Write Strobe) signal allows the initiator to indicate which specific bytes of the WDATA bus contain valid information for the current beat.

When should a WRAP burst be used instead of an INCR burst?

WRAP bursts are used when the system needs to access a sequential block of memory but must wrap around to the start of the boundary once the end is reached, which is common in cache line operations.

What is the difference between the Write Data channel and the Write Response channel?

The Write Data channel is used by the initiator to send the actual payload to the target, while the Write Response channel is used by the target to confirm whether the write operation was successful.